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// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
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// 
// Device: Altera EP3C16F484C6 Package FBGA484
// 

//
// This file contains Slow Corner delays for the design using part EP3C16F484C6,
// with speed grade 6, core voltage 1.2V, and temperature 0 Celsius
//

// 
// This SDF file should be used for ModelSim (Verilog) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "parallel_load_shift_register")
  (DATE "05/22/2022 23:04:12")
  (VENDOR "Altera")
  (PROGRAM "Quartus II 64-Bit")
  (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition")
  (DIVIDER .)
  (TIMESCALE 1 ps)

	// No Timing Cells with timing info are found in the compiled design. A dummy “dff” Timing Cell is created.
  (CELL
    (CELLTYPE "dff")
    (INSTANCE * )
  )
	// No Timing Cells with timing info are found in the compiled design. A dummy “dff” Timing Cell is created.
  (CELL
    (CELLTYPE "dff")
    (INSTANCE * )
  )
)
