// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"

// DATE "05/22/2022 23:04:12"

// 
// Device: Altera EP3C16F484C6 Package FBGA484
// 

// 
// This Verilog file should be used for ModelSim (Verilog) only
// 

`timescale 1 ps/ 1 ps

module parallel_load_shift_register (
	Q,
	ones_out,
	I7,
	I6,
	I5,
	I4,
	I3,
	I2,
	I1,
	I0,
	load,
	enable,
	reset,
	Clk);
output 	[7:0] Q;
output 	[3:0] ones_out;
input 	I7;
input 	I6;
input 	I5;
input 	I4;
input 	I3;
input 	I2;
input 	I1;
input 	I0;
input 	load;
input 	enable;
input 	reset;
input 	Clk;

// Design Ports Information
// Q[0]	=>  Location: PIN_T10,	 I/O Standard: 2.5 V,	 Current Strength: Default
// Q[1]	=>  Location: PIN_L8,	 I/O Standard: 2.5 V,	 Current Strength: Default
// Q[2]	=>  Location: PIN_L21,	 I/O Standard: 2.5 V,	 Current Strength: Default
// Q[3]	=>  Location: PIN_AA16,	 I/O Standard: 2.5 V,	 Current Strength: Default
// Q[4]	=>  Location: PIN_B1,	 I/O Standard: 2.5 V,	 Current Strength: Default
// Q[5]	=>  Location: PIN_D15,	 I/O Standard: 2.5 V,	 Current Strength: Default
// Q[6]	=>  Location: PIN_Y2,	 I/O Standard: 2.5 V,	 Current Strength: Default
// Q[7]	=>  Location: PIN_AB7,	 I/O Standard: 2.5 V,	 Current Strength: Default
// ones_out[0]	=>  Location: PIN_F9,	 I/O Standard: 2.5 V,	 Current Strength: Default
// ones_out[1]	=>  Location: PIN_V6,	 I/O Standard: 2.5 V,	 Current Strength: Default
// ones_out[2]	=>  Location: PIN_F2,	 I/O Standard: 2.5 V,	 Current Strength: Default
// ones_out[3]	=>  Location: PIN_T5,	 I/O Standard: 2.5 V,	 Current Strength: Default
// I7	=>  Location: PIN_T12,	 I/O Standard: 2.5 V,	 Current Strength: Default
// I6	=>  Location: PIN_M1,	 I/O Standard: 2.5 V,	 Current Strength: Default
// I5	=>  Location: PIN_C2,	 I/O Standard: 2.5 V,	 Current Strength: Default
// I4	=>  Location: PIN_J22,	 I/O Standard: 2.5 V,	 Current Strength: Default
// I3	=>  Location: PIN_J6,	 I/O Standard: 2.5 V,	 Current Strength: Default
// I2	=>  Location: PIN_E1,	 I/O Standard: 2.5 V,	 Current Strength: Default
// I1	=>  Location: PIN_G11,	 I/O Standard: 2.5 V,	 Current Strength: Default
// I0	=>  Location: PIN_AA20,	 I/O Standard: 2.5 V,	 Current Strength: Default
// load	=>  Location: PIN_G4,	 I/O Standard: 2.5 V,	 Current Strength: Default
// enable	=>  Location: PIN_G3,	 I/O Standard: 2.5 V,	 Current Strength: Default
// reset	=>  Location: PIN_H1,	 I/O Standard: 2.5 V,	 Current Strength: Default
// Clk	=>  Location: PIN_W20,	 I/O Standard: 2.5 V,	 Current Strength: Default


wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
// synopsys translate_off
initial $sdf_annotate("parallel_load_shift_register_6_1200mv_85c_v_slow.sdo");
// synopsys translate_on

wire \I7~input_o ;
wire \I6~input_o ;
wire \I5~input_o ;
wire \I4~input_o ;
wire \I3~input_o ;
wire \I2~input_o ;
wire \I1~input_o ;
wire \I0~input_o ;
wire \load~input_o ;
wire \enable~input_o ;
wire \reset~input_o ;
wire \Clk~input_o ;
wire \Q[0]~output_o ;
wire \Q[1]~output_o ;
wire \Q[2]~output_o ;
wire \Q[3]~output_o ;
wire \Q[4]~output_o ;
wire \Q[5]~output_o ;
wire \Q[6]~output_o ;
wire \Q[7]~output_o ;
wire \ones_out[0]~output_o ;
wire \ones_out[1]~output_o ;
wire \ones_out[2]~output_o ;
wire \ones_out[3]~output_o ;


// Location: IOOBUF_X14_Y0_N9
cycloneiii_io_obuf \Q[0]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\Q[0]~output_o ),
	.obar());
// synopsys translate_off
defparam \Q[0]~output .bus_hold = "false";
defparam \Q[0]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X0_Y22_N2
cycloneiii_io_obuf \Q[1]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\Q[1]~output_o ),
	.obar());
// synopsys translate_off
defparam \Q[1]~output .bus_hold = "false";
defparam \Q[1]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X41_Y18_N16
cycloneiii_io_obuf \Q[2]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\Q[2]~output_o ),
	.obar());
// synopsys translate_off
defparam \Q[2]~output .bus_hold = "false";
defparam \Q[2]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X28_Y0_N23
cycloneiii_io_obuf \Q[3]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\Q[3]~output_o ),
	.obar());
// synopsys translate_off
defparam \Q[3]~output .bus_hold = "false";
defparam \Q[3]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X0_Y27_N16
cycloneiii_io_obuf \Q[4]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\Q[4]~output_o ),
	.obar());
// synopsys translate_off
defparam \Q[4]~output .bus_hold = "false";
defparam \Q[4]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X32_Y29_N30
cycloneiii_io_obuf \Q[5]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\Q[5]~output_o ),
	.obar());
// synopsys translate_off
defparam \Q[5]~output .bus_hold = "false";
defparam \Q[5]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X0_Y6_N2
cycloneiii_io_obuf \Q[6]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\Q[6]~output_o ),
	.obar());
// synopsys translate_off
defparam \Q[6]~output .bus_hold = "false";
defparam \Q[6]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X11_Y0_N9
cycloneiii_io_obuf \Q[7]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\Q[7]~output_o ),
	.obar());
// synopsys translate_off
defparam \Q[7]~output .bus_hold = "false";
defparam \Q[7]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X7_Y29_N23
cycloneiii_io_obuf \ones_out[0]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\ones_out[0]~output_o ),
	.obar());
// synopsys translate_off
defparam \ones_out[0]~output .bus_hold = "false";
defparam \ones_out[0]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X1_Y0_N2
cycloneiii_io_obuf \ones_out[1]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\ones_out[1]~output_o ),
	.obar());
// synopsys translate_off
defparam \ones_out[1]~output .bus_hold = "false";
defparam \ones_out[1]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X0_Y24_N23
cycloneiii_io_obuf \ones_out[2]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\ones_out[2]~output_o ),
	.obar());
// synopsys translate_off
defparam \ones_out[2]~output .bus_hold = "false";
defparam \ones_out[2]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X0_Y3_N2
cycloneiii_io_obuf \ones_out[3]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\ones_out[3]~output_o ),
	.obar());
// synopsys translate_off
defparam \ones_out[3]~output .bus_hold = "false";
defparam \ones_out[3]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOIBUF_X28_Y0_N29
cycloneiii_io_ibuf \I7~input (
	.i(I7),
	.ibar(gnd),
	.o(\I7~input_o ));
// synopsys translate_off
defparam \I7~input .bus_hold = "false";
defparam \I7~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X0_Y13_N22
cycloneiii_io_ibuf \I6~input (
	.i(I6),
	.ibar(gnd),
	.o(\I6~input_o ));
// synopsys translate_off
defparam \I6~input .bus_hold = "false";
defparam \I6~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X0_Y26_N15
cycloneiii_io_ibuf \I5~input (
	.i(I5),
	.ibar(gnd),
	.o(\I5~input_o ));
// synopsys translate_off
defparam \I5~input .bus_hold = "false";
defparam \I5~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X41_Y19_N1
cycloneiii_io_ibuf \I4~input (
	.i(I4),
	.ibar(gnd),
	.o(\I4~input_o ));
// synopsys translate_off
defparam \I4~input .bus_hold = "false";
defparam \I4~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X0_Y24_N1
cycloneiii_io_ibuf \I3~input (
	.i(I3),
	.ibar(gnd),
	.o(\I3~input_o ));
// synopsys translate_off
defparam \I3~input .bus_hold = "false";
defparam \I3~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X0_Y24_N15
cycloneiii_io_ibuf \I2~input (
	.i(I2),
	.ibar(gnd),
	.o(\I2~input_o ));
// synopsys translate_off
defparam \I2~input .bus_hold = "false";
defparam \I2~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X14_Y29_N15
cycloneiii_io_ibuf \I1~input (
	.i(I1),
	.ibar(gnd),
	.o(\I1~input_o ));
// synopsys translate_off
defparam \I1~input .bus_hold = "false";
defparam \I1~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X37_Y0_N22
cycloneiii_io_ibuf \I0~input (
	.i(I0),
	.ibar(gnd),
	.o(\I0~input_o ));
// synopsys translate_off
defparam \I0~input .bus_hold = "false";
defparam \I0~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X0_Y23_N8
cycloneiii_io_ibuf \load~input (
	.i(load),
	.ibar(gnd),
	.o(\load~input_o ));
// synopsys translate_off
defparam \load~input .bus_hold = "false";
defparam \load~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X0_Y23_N15
cycloneiii_io_ibuf \enable~input (
	.i(enable),
	.ibar(gnd),
	.o(\enable~input_o ));
// synopsys translate_off
defparam \enable~input .bus_hold = "false";
defparam \enable~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X0_Y21_N15
cycloneiii_io_ibuf \reset~input (
	.i(reset),
	.ibar(gnd),
	.o(\reset~input_o ));
// synopsys translate_off
defparam \reset~input .bus_hold = "false";
defparam \reset~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X41_Y3_N15
cycloneiii_io_ibuf \Clk~input (
	.i(Clk),
	.ibar(gnd),
	.o(\Clk~input_o ));
// synopsys translate_off
defparam \Clk~input .bus_hold = "false";
defparam \Clk~input .simulate_z_as = "z";
// synopsys translate_on

assign Q[0] = \Q[0]~output_o ;

assign Q[1] = \Q[1]~output_o ;

assign Q[2] = \Q[2]~output_o ;

assign Q[3] = \Q[3]~output_o ;

assign Q[4] = \Q[4]~output_o ;

assign Q[5] = \Q[5]~output_o ;

assign Q[6] = \Q[6]~output_o ;

assign Q[7] = \Q[7]~output_o ;

assign ones_out[0] = \ones_out[0]~output_o ;

assign ones_out[1] = \ones_out[1]~output_o ;

assign ones_out[2] = \ones_out[2]~output_o ;

assign ones_out[3] = \ones_out[3]~output_o ;

endmodule
