module D_FF_R_L(Q, D, Clk,rst,load);
output Q;
input D, Clk,rst,load;
reg Q;
// on the rising edge of the clock
always @ (posedge Clk)
begin
Q <= D;
if(rst==0)
	Q<=0;
else if(rst!=0&&load==1)
	Q<=D;
else if(rst!=0&&load==0)
	Q<=Q;
end
endmodule
 