Analysis & Synthesis report for parallel_load_shift_register
Tue May 24 22:53:51 2022
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
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+--------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                         ;
+------------------------------------+-------------------------------------------------+
; Analysis & Synthesis Status        ; Failed - Tue May 24 22:53:51 2022               ;
; Quartus II 64-Bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name                      ; parallel_load_shift_register                    ;
; Top-level Entity Name              ; parallel_load_shift_register                    ;
; Family                             ; Cyclone III                                     ;
; Total logic elements               ; N/A until Partition Merge                       ;
;     Total combinational functions  ; N/A until Partition Merge                       ;
;     Dedicated logic registers      ; N/A until Partition Merge                       ;
; Total registers                    ; N/A until Partition Merge                       ;
; Total pins                         ; N/A until Partition Merge                       ;
; Total virtual pins                 ; N/A until Partition Merge                       ;
; Total memory bits                  ; N/A until Partition Merge                       ;
; Embedded Multiplier 9-bit elements ; N/A until Partition Merge                       ;
; Total PLLs                         ; N/A until Partition Merge                       ;
+------------------------------------+-------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                                            ;
+----------------------------------------------------------------------------+------------------------------+------------------------------+
; Option                                                                     ; Setting                      ; Default Value                ;
+----------------------------------------------------------------------------+------------------------------+------------------------------+
; Device                                                                     ; EP3C16F484C6                 ;                              ;
; Top-level entity name                                                      ; parallel_load_shift_register ; parallel_load_shift_register ;
; Family name                                                                ; Cyclone III                  ; Cyclone IV GX                ;
; Use smart compilation                                                      ; Off                          ; Off                          ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                           ; On                           ;
; Enable compact report table                                                ; Off                          ; Off                          ;
; Restructure Multiplexers                                                   ; Auto                         ; Auto                         ;
; Create Debugging Nodes for IP Cores                                        ; Off                          ; Off                          ;
; Preserve fewer node names                                                  ; On                           ; On                           ;
; Disable OpenCore Plus hardware evaluation                                  ; Off                          ; Off                          ;
; Verilog Version                                                            ; Verilog_2001                 ; Verilog_2001                 ;
; VHDL Version                                                               ; VHDL_1993                    ; VHDL_1993                    ;
; State Machine Processing                                                   ; Auto                         ; Auto                         ;
; Safe State Machine                                                         ; Off                          ; Off                          ;
; Extract Verilog State Machines                                             ; On                           ; On                           ;
; Extract VHDL State Machines                                                ; On                           ; On                           ;
; Ignore Verilog initial constructs                                          ; Off                          ; Off                          ;
; Iteration limit for constant Verilog loops                                 ; 5000                         ; 5000                         ;
; Iteration limit for non-constant Verilog loops                             ; 250                          ; 250                          ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On                           ; On                           ;
; Infer RAMs from Raw Logic                                                  ; On                           ; On                           ;
; Parallel Synthesis                                                         ; On                           ; On                           ;
; DSP Block Balancing                                                        ; Auto                         ; Auto                         ;
; NOT Gate Push-Back                                                         ; On                           ; On                           ;
; Power-Up Don't Care                                                        ; On                           ; On                           ;
; Remove Redundant Logic Cells                                               ; Off                          ; Off                          ;
; Remove Duplicate Registers                                                 ; On                           ; On                           ;
; Ignore CARRY Buffers                                                       ; Off                          ; Off                          ;
; Ignore CASCADE Buffers                                                     ; Off                          ; Off                          ;
; Ignore GLOBAL Buffers                                                      ; Off                          ; Off                          ;
; Ignore ROW GLOBAL Buffers                                                  ; Off                          ; Off                          ;
; Ignore LCELL Buffers                                                       ; Off                          ; Off                          ;
; Ignore SOFT Buffers                                                        ; On                           ; On                           ;
; Limit AHDL Integers to 32 Bits                                             ; Off                          ; Off                          ;
; Optimization Technique                                                     ; Balanced                     ; Balanced                     ;
; Carry Chain Length                                                         ; 70                           ; 70                           ;
; Auto Carry Chains                                                          ; On                           ; On                           ;
; Auto Open-Drain Pins                                                       ; On                           ; On                           ;
; Perform WYSIWYG Primitive Resynthesis                                      ; Off                          ; Off                          ;
; Auto ROM Replacement                                                       ; On                           ; On                           ;
; Auto RAM Replacement                                                       ; On                           ; On                           ;
; Auto DSP Block Replacement                                                 ; On                           ; On                           ;
; Auto Shift Register Replacement                                            ; Auto                         ; Auto                         ;
; Allow Shift Register Merging across Hierarchies                            ; Auto                         ; Auto                         ;
; Auto Clock Enable Replacement                                              ; On                           ; On                           ;
; Strict RAM Replacement                                                     ; Off                          ; Off                          ;
; Allow Synchronous Control Signals                                          ; On                           ; On                           ;
; Force Use of Synchronous Clear Signals                                     ; Off                          ; Off                          ;
; Auto RAM Block Balancing                                                   ; On                           ; On                           ;
; Auto RAM to Logic Cell Conversion                                          ; Off                          ; Off                          ;
; Auto Resource Sharing                                                      ; Off                          ; Off                          ;
; Allow Any RAM Size For Recognition                                         ; Off                          ; Off                          ;
; Allow Any ROM Size For Recognition                                         ; Off                          ; Off                          ;
; Allow Any Shift Register Size For Recognition                              ; Off                          ; Off                          ;
; Use LogicLock Constraints during Resource Balancing                        ; On                           ; On                           ;
; Ignore translate_off and synthesis_off directives                          ; Off                          ; Off                          ;
; Timing-Driven Synthesis                                                    ; On                           ; On                           ;
; Report Parameter Settings                                                  ; On                           ; On                           ;
; Report Source Assignments                                                  ; On                           ; On                           ;
; Report Connectivity Checks                                                 ; On                           ; On                           ;
; Ignore Maximum Fan-Out Assignments                                         ; Off                          ; Off                          ;
; Synchronization Register Chain Length                                      ; 2                            ; 2                            ;
; PowerPlay Power Optimization                                               ; Normal compilation           ; Normal compilation           ;
; HDL message level                                                          ; Level2                       ; Level2                       ;
; Suppress Register Optimization Related Messages                            ; Off                          ; Off                          ;
; Number of Removed Registers Reported in Synthesis Report                   ; 5000                         ; 5000                         ;
; Number of Swept Nodes Reported in Synthesis Report                         ; 5000                         ; 5000                         ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100                          ; 100                          ;
; Clock MUX Protection                                                       ; On                           ; On                           ;
; Auto Gated Clock Conversion                                                ; Off                          ; Off                          ;
; Block Design Naming                                                        ; Auto                         ; Auto                         ;
; SDC constraint protection                                                  ; Off                          ; Off                          ;
; Synthesis Effort                                                           ; Auto                         ; Auto                         ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                           ; On                           ;
; Pre-Mapping Resynthesis Optimization                                       ; Off                          ; Off                          ;
; Analysis & Synthesis Message Level                                         ; Medium                       ; Medium                       ;
; Disable Register Merging Across Hierarchies                                ; Auto                         ; Auto                         ;
; Resource Aware Inference For Block RAM                                     ; On                           ; On                           ;
; Synthesis Seed                                                             ; 1                            ; 1                            ;
+----------------------------------------------------------------------------+------------------------------+------------------------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 12     ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Processing started: Tue May 24 22:53:50 2022
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off parallel_load_shift_register -c parallel_load_shift_register
Warning (20028): Parallel compilation is not licensed and has been disabled
Error (10170): Verilog HDL syntax error at parallel_load_shift_register.v(47) near text "while";  expecting "end" File: C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/parallel_load_shift_register.v Line: 47
Error (10170): Verilog HDL syntax error at parallel_load_shift_register.v(47) near text "==";  expecting ".", or an identifier File: C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/parallel_load_shift_register.v Line: 47
Error (10170): Verilog HDL syntax error at parallel_load_shift_register.v(48) near text "1";  expecting an identifier File: C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/parallel_load_shift_register.v Line: 48
Error (10112): Ignored design unit "top" at parallel_load_shift_register.v(37) due to previous errors File: C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/parallel_load_shift_register.v Line: 37
Info (12021): Found 0 design units, including 0 entities, in source file parallel_load_shift_register.v
Info (12021): Found 1 design units, including 1 entities, in source file d_ff_r_l.v
    Info (12023): Found entity 1: D_FF_R_L
Info (12021): Found 1 design units, including 1 entities, in source file two_one_mux.v
    Info (12023): Found entity 1: two_one_mux
Info (12021): Found 1 design units, including 1 entities, in source file four_bit_up_down_counter.v
    Info (12023): Found entity 1: four_bit_up_down_counter
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 4 errors, 1 warning
    Error: Peak virtual memory: 4565 megabytes
    Error: Processing ended: Tue May 24 22:53:51 2022
    Error: Elapsed time: 00:00:01
    Error: Total CPU time (on all processors): 00:00:00


