{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1653249845191 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "parallel_load_shift_register EP3C16F484C6 " "Selected device EP3C16F484C6 for design \"parallel_load_shift_register\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1653249845191 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1653249845222 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1653249845222 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1653249845222 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1653249845269 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1653249845269 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40F484C6 " "Device EP3C40F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1653249845423 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55F484C6 " "Device EP3C55F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1653249845423 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80F484C6 " "Device EP3C80F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1653249845423 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1653249845423 ""}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/" { { 0 { 0 ""} 0 66 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1653249845424 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/" { { 0 { 0 ""} 0 68 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1653249845424 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/" { { 0 { 0 ""} 0 70 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1653249845424 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/" { { 0 { 0 ""} 0 72 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1653249845424 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/" { { 0 { 0 ""} 0 74 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1653249845424 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1653249845424 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1653249845425 ""}
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "24 24 " "No exact pin location assignment(s) for 24 pins of 24 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Q\[0\] " "Pin Q\[0\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { Q[0] } } } { "parallel_load_shift_register.v" "" { Text "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/parallel_load_shift_register.v" 5 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Q[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/" { { 0 { 0 ""} 0 13 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1653249845920 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Q\[1\] " "Pin Q\[1\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { Q[1] } } } { "parallel_load_shift_register.v" "" { Text "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/parallel_load_shift_register.v" 5 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Q[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/" { { 0 { 0 ""} 0 14 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1653249845920 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Q\[2\] " "Pin Q\[2\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { Q[2] } } } { "parallel_load_shift_register.v" "" { Text "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/parallel_load_shift_register.v" 5 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Q[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/" { { 0 { 0 ""} 0 15 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1653249845920 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Q\[3\] " "Pin Q\[3\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { Q[3] } } } { "parallel_load_shift_register.v" "" { Text "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/parallel_load_shift_register.v" 5 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Q[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/" { { 0 { 0 ""} 0 16 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1653249845920 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Q\[4\] " "Pin Q\[4\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { Q[4] } } } { "parallel_load_shift_register.v" "" { Text "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/parallel_load_shift_register.v" 5 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Q[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/" { { 0 { 0 ""} 0 17 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1653249845920 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Q\[5\] " "Pin Q\[5\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { Q[5] } } } { "parallel_load_shift_register.v" "" { Text "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/parallel_load_shift_register.v" 5 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Q[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/" { { 0 { 0 ""} 0 18 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1653249845920 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Q\[6\] " "Pin Q\[6\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { Q[6] } } } { "parallel_load_shift_register.v" "" { Text "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/parallel_load_shift_register.v" 5 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Q[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/" { { 0 { 0 ""} 0 19 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1653249845920 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Q\[7\] " "Pin Q\[7\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { Q[7] } } } { "parallel_load_shift_register.v" "" { Text "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/parallel_load_shift_register.v" 5 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Q[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/" { { 0 { 0 ""} 0 20 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1653249845920 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "ones_out\[0\] " "Pin ones_out\[0\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ones_out[0] } } } { "parallel_load_shift_register.v" "" { Text "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/parallel_load_shift_register.v" 6 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ones_out[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/" { { 0 { 0 ""} 0 21 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1653249845920 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "ones_out\[1\] " "Pin ones_out\[1\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ones_out[1] } } } { "parallel_load_shift_register.v" "" { Text "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/parallel_load_shift_register.v" 6 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ones_out[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/" { { 0 { 0 ""} 0 22 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1653249845920 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "ones_out\[2\] " "Pin ones_out\[2\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ones_out[2] } } } { "parallel_load_shift_register.v" "" { Text "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/parallel_load_shift_register.v" 6 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ones_out[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/" { { 0 { 0 ""} 0 23 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1653249845920 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "ones_out\[3\] " "Pin ones_out\[3\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ones_out[3] } } } { "parallel_load_shift_register.v" "" { Text "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/parallel_load_shift_register.v" 6 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ones_out[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/" { { 0 { 0 ""} 0 24 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1653249845920 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "I7 " "Pin I7 not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { I7 } } } { "parallel_load_shift_register.v" "" { Text "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/parallel_load_shift_register.v" 2 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { I7 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/" { { 0 { 0 ""} 0 25 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1653249845920 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "I6 " "Pin I6 not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { I6 } } } { "parallel_load_shift_register.v" "" { Text "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/parallel_load_shift_register.v" 2 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { I6 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/" { { 0 { 0 ""} 0 26 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1653249845920 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "I5 " "Pin I5 not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { I5 } } } { "parallel_load_shift_register.v" "" { Text "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/parallel_load_shift_register.v" 2 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { I5 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/" { { 0 { 0 ""} 0 27 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1653249845920 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "I4 " "Pin I4 not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { I4 } } } { "parallel_load_shift_register.v" "" { Text "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/parallel_load_shift_register.v" 2 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { I4 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/" { { 0 { 0 ""} 0 28 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1653249845920 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "I3 " "Pin I3 not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { I3 } } } { "parallel_load_shift_register.v" "" { Text "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/parallel_load_shift_register.v" 2 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { I3 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/" { { 0 { 0 ""} 0 29 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1653249845920 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "I2 " "Pin I2 not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { I2 } } } { "parallel_load_shift_register.v" "" { Text "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/parallel_load_shift_register.v" 2 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { I2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/" { { 0 { 0 ""} 0 30 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1653249845920 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "I1 " "Pin I1 not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { I1 } } } { "parallel_load_shift_register.v" "" { Text "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/parallel_load_shift_register.v" 2 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { I1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/" { { 0 { 0 ""} 0 31 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1653249845920 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "I0 " "Pin I0 not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { I0 } } } { "parallel_load_shift_register.v" "" { Text "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/parallel_load_shift_register.v" 2 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { I0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/" { { 0 { 0 ""} 0 32 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1653249845920 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "load " "Pin load not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { load } } } { "parallel_load_shift_register.v" "" { Text "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/parallel_load_shift_register.v" 2 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { load } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/" { { 0 { 0 ""} 0 33 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1653249845920 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "enable " "Pin enable not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { enable } } } { "parallel_load_shift_register.v" "" { Text "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/parallel_load_shift_register.v" 2 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { enable } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/" { { 0 { 0 ""} 0 34 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1653249845920 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "reset " "Pin reset not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { reset } } } { "parallel_load_shift_register.v" "" { Text "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/parallel_load_shift_register.v" 2 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/" { { 0 { 0 ""} 0 35 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1653249845920 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Clk " "Pin Clk not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { Clk } } } { "parallel_load_shift_register.v" "" { Text "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/parallel_load_shift_register.v" 2 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Clk } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/" { { 0 { 0 ""} 0 36 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1653249845920 ""}  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1653249845920 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "parallel_load_shift_register.sdc " "Synopsys Design Constraints File file not found: 'parallel_load_shift_register.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1653249846014 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1653249846014 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Fitter" 0 -1 1653249846014 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1653249846014 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1653249846014 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1653249846014 ""}
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1653249846014 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1653249846014 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1653249846014 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1653249846014 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1653249846014 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1653249846014 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1653249846014 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1653249846014 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1653249846014 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1653249846014 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1653249846014 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1653249846014 ""}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "24 unused 2.5V 12 12 0 " "Number of I/O pins in group: 24 (unused VREF, 2.5V VCCIO, 12 input, 12 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1653249846014 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1653249846014 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1653249846014 ""}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 4 29 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used --  29 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1653249846014 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 48 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1653249846014 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 46 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1653249846014 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 41 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  41 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1653249846014 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 46 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1653249846014 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 42 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  42 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1653249846014 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 47 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  47 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1653249846014 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  43 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1653249846014 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1653249846014 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1653249846014 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1653249846029 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1653249846592 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1653249846623 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1653249846623 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1653249846717 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1653249846717 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1653249846888 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y20 X9_Y29 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29" {  } { { "loc" "" { Generic "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} 0 20 10 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1653249847154 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1653249847154 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1653249847201 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1653249847201 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1653249847201 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1653249847201 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.03 " "Total time spent on timing analysis during the Fitter is 0.03 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1653249847201 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1653249847232 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1653249847419 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1653249847435 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1653249847623 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1653249847841 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/output_files/parallel_load_shift_register.fit.smsg " "Generated suppressed messages file C:/Users/simay/OneDrive/Masaüstü/ODTÜ 3. Dönem/EEE248/Lab 4 and 5/Parallel_Load_Shift_Register Verilog Code/output_files/parallel_load_shift_register.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1653249848357 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4825 " "Peak virtual memory: 4825 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1653249848513 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 22 23:04:08 2022 " "Processing ended: Sun May 22 23:04:08 2022" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1653249848513 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1653249848513 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1653249848513 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1653249848513 ""}
