module parallel_load_shift_register(Q,ones_out,I7,I6,I5,I4,I3,I2,I1,I0,load,enable,reset,Clk);
input I7,I6,I5,I4,I3,I2,I1,I0,load,enable,reset,Clk;
wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13,w14,w15,w16;
reg w17,w18,w19,w20,w21,w22,w23,w24;
output [7:0] Q;
output [3:0] ones_out;//Number of ones output

D_FF_R_L U1(Q[7],w17,Clk, rst,load);//Böyle olmuyor sanırım. Daha sonra Q[7] yi bir wire a eÅŸitlersin.

D_FF_R_L U2(Q[6],w18,Clk, rst,load);

D_FF_R_L U3(Q[5],w19,Clk, rst,load);

D_FF_R_L U4(Q[4],w20,Clk, rst,load);

D_FF_R_L U5(Q[3],w21,Clk, rst,load);

D_FF_R_L U6(Q[2],w22,Clk, rst,load);

D_FF_R_L U7(Q[1],w23,Clk, rst,load);

D_FF_R_L U8(Q[0],w24,Clk, rst,load);

always@(posedge Clk)
begin
w17 <= ((Q[7]&(~load))|(I7&load));
w18 <= ((Q[6]&(~load))|(I6&load));
w19 <= ((Q[5]&(~load))|(I5&load));
w20 <= ((Q[4]&(~load))|(I4&load));
w21 <= ((Q[3]&(~load))|(I3&load));
w22 <= ((Q[2]&(~load))|(I2&load));
w23 <= ((Q[1]&(~load))|(I1&load));
w24 <= ((Q[0]&(~load))|(I0&load));
end
endmodule 