All Logic Gates Verilog VHDL and ModelSim Codes

All Logic Gates Verilog VHDL and ModelSim Codes The purpose of the first laboratory exercise is getting familiar with Quartus II Project Navigator, DEO Demo Board, and the associated toolset to facilitate the digital logic design. The student will complete a step-by-step tutorial in the first part of the experiment to implement complex gates (XOR, NAND, NOR) on a Cyclone III FPGA (Field Programmable Gate Array) using schematic entry, simulation, and FPGA programming tools. Verilog will be utilised in the second part of the experiment to implement a 1-bit full adder designed in the preliminary work. The relationship between majority-voter, odd-detector and full- adder logic will also be studied.

Complex Gates Verilog VHDL and ModelSim Codes

Table 1 (a-b) provide the truth tables corresponding to a 3-input minority gate and 3-input even- detector. Table 1:1.2.3. Complex Gates (a) 3-input Minory Gate (b) 3-input Even Detector

Bakery Profit Calculator Verilog VHDL and ModelSim Codes

In this design, you will implement a simple digital circuit to compute total profits made by a bakery based on the kinds of deserts that they are baking. Bakery owner has to follow the set of guidelines below for setting up the bakery. 1. Baker can bake donuts, brownies, eclairs, and croissants on his bakery but cannot produce all at the same time. 2. The bakery does not have enough space to bake more than 2 different types of deserts. Therefore, his bakery never has more than 2 types of deserts at any particular time.

Adder/Subtractor Verilog VHDL and ModelSim Codes

This lab will expand on the design entry knowledge gained in the last lab by designing fundamental combinational circuits for use by the Arithmetic Logic Unit (ALU). ALU is a common digital logic circuit that performs arithmetic, logical, and comparison operations between inputs on most microcontrollers, microprocessors, and DSPs. Combinational circuits such as adders, multiplexers, comparator, and decoder circuits, which are utilized to form ALU, will be designed in LAB 2 and LAB 3.

Comparator Verilog VHDL and ModelSim Codes

This lab will expand on the design entry knowledge gained in the last lab by designing fundamental combinational circuits for use by the Arithmetic Logic Unit (ALU). ALU is a common digital logic circuit that performs arithmetic, logical, and comparison operations between inputs on most microcontrollers, microprocessors, and DSPs. Combinational circuits such as adders, multiplexers, comparator, and decoder circuits, which are utilized to form ALU, will be designed in LAB 2 and LAB 3.

Decoder Verilog VHDL and ModelSim Codes

This lab will expand on the design entry knowledge gained in the last lab by designing fundamental combinational circuits for use by the Arithmetic Logic Unit (ALU). ALU is a common digital logic circuit that performs arithmetic, logical, and comparison operations between inputs on most microcontrollers, microprocessors, and DSPs. Combinational circuits such as adders, multiplexers, comparator, and decoder circuits, which are utilized to form ALU, will be designed in LAB 2 and LAB 3.

Full Adder Verilog VHDL and ModelSim Codes

This lab will expand on the design entry knowledge gained in the last lab by designing fundamental combinational circuits for use by the Arithmetic Logic Unit (ALU). ALU is a common digital logic circuit that performs arithmetic, logical, and comparison operations between inputs on most microcontrollers, microprocessors, and DSPs. Combinational circuits such as adders, multiplexers, comparator, and decoder circuits, which are utilized to form ALU, will be designed in LAB 2 and LAB 3.

Ripple Carry Adder Verilog VHDL and ModelSim Codes

This lab will expand on the design entry knowledge gained in the last lab by designing fundamental combinational circuits for use by the Arithmetic Logic Unit (ALU). ALU is a common digital logic circuit that performs arithmetic, logical, and comparison operations between inputs on most microcontrollers, microprocessors, and DSPs. Combinational circuits such as adders, multiplexers, comparator, and decoder circuits, which are utilized to form ALU, will be designed in LAB 2 and LAB 3.

Arithmetic Unit Verilog VHDL and ModelSim Codes

After a 4-bit Adder/Subtractor and a 4-bit Comparator module have been implemented and tested in 2.2.3 and 2.2.4, combine these two modules as shown in Figure 5 in one structural Verilog HDL design named as ARITHMETIC_UNIT.

Logic Unit Verilog VHDL and ModelSim Codes

In the fourth part of the experiment basic logic gates designed in LAB 1 will be combined with multiplexers to be used as a logic unit of ALU. In the fifth part of the experiment, multiplexers will be designed to choose the operation either from arithmetic unit or from logic unit (ADD/SUB, AND, OR, NAND, NOR, XOR, XNOR, NOTA, NOTB). Finally, all of the Verilog HDL design modules will be integrated in the top-level design to implement complete ALU design as depicted in Figure 2.

In the fourth part of the experiment basic logic gates designed in LAB 1 will be combined with multiplexers to be used as a logic unit of ALU. In the fifth part of the experiment, multiplexers will be designed to choose the operation either from arithmetic unit or from logic unit (ADD/SUB, AND, OR, NAND, NOR, XOR, XNOR, NOTA, NOTB). Finally, all of the Verilog HDL design modules will be integrated in the top-level design to implement complete ALU design as depicted in Figure 2.

Arithmetic Logic Unit Verilog VHDL and ModelSim Codes

In the fourth part of the experiment basic logic gates designed in LAB 1 will be combined with multiplexers to be used as a Logic unit of ALU. In the fifth part of the experiment, multiplexers will be designed to choose the operation either from arithmetic unit or from Logic unit (ADD/SUB, AND, OR, NAND, NOR, XOR, XNOR, NOTA, NOTB). Finally, all of the Verilog HDL design modules will be integrated in the top-level design to implement complete ALU design as depicted in Figure 2.

1. Refer to your ModelsimR tutorial and create a project in ModelSim®, simulate your Verilog design and the testbench and check your waveform to verify the functionality of your design. a. When defining the test bench waveform for functional simulation, make sure the test is long enough. Carefully define your vectors for your inputs and run exhaustive tests to test each possible combination. 2. Demonstrate the functionality of your design in ModelSimR to the lab instructor before proceeding. 3. Launch Quartus II Project Navigator. 4. Create a project named your_nameALU, enter the complete combinational design using Schematic Capture, simulate, download program to FPGA and test. a. Refer to section 2.4.2 to pull in all the previous design modules into the current project and create a symbol for each module. b. Instantiate the symbols for the design modules, interconnect and assign I/O ports. Pay attention to multi-bit vs. single-bit wires and naming conventions as described in 2.4.3 c. Ensure in functional and timing simulations that your design works correctly before programming to the FPGA. Then program and test the same vectors as in (iii) above to make sure you get the same results as your functional simulations. If you do not have a sufficient number of switches to implement your inputs, remember you can also take advantage of push buttons on DEO board as inputs.

D Flip-Flop Verilog VHDL and ModelSim Codes

Draw a schematic to show how you would add combinational logic along with two new inputs (R and L) to a conventional D Flip-Flop to have the Reset and Load functions as shown in Figure 1. Note Load input take effect synchronously on the rising edge of the clock and Reset input is an active low input that takes effect asynchronously.

Shift Register Verilog VHDL and ModelSim Codes

Use the new D Flip-Flop in Figure 1 and design a 4-bit scalable bit-sliced synchronous shift register (with SI input and SO output) with synchronous Load and asynchronous Reset. The symbol and a table that describes the operation of the register are depicted in Figure 2. The register has four input and one output. Write a structural (hierarchical) Verilog HDL code by explicitly declaring the D Flip-Flop created in 4.2.2. Do not use if statement (behavioural) approach. Use the following test patterns with the clock periods provided in Table 1. Write a Verilog Testbench code to simulate and verify the functionality in ModelSim.

Up-Down Counter Verilog VHDL and ModelSim Codes

Write a structural (hierarchical) Verilog HDL code by explicitly declaring the D Flip-Flop to create a scalable design of a 4-bit synchronous wrap-around up/down counter with synchronous up/down select and count-enable controls, and asynchronous reset as depicted in Figure 3. Do not use if statement (behavioural) approach.

Down Counter With D-Type FF Verilog VHDL and ModelSim Codes

3-BIT DOWN COUNTER USING D-TYPE FLIP-FLOP Design a 3-bit down counter with asynchronous clear using rising-edge triggered D-type flip-flops. The count should wrap around from “000” to “111”.

Down Counter With JK-Type FF Verilog VHDL and ModelSim Codes

3-BIT DOWN COUNTER USING JK-TYPE FLIP-FLOP Design a 3-bit down counter with asynchronous clear using negative-edge triggered JK-type flip-flops with asynchronous active low clear.

Paralel Load Shift Register Verilog VHDL and ModelSim Codes

4-BIT SYNCHRONOUS PARALLEL LOAD SHIFT REGISTER WITH COUNTER AND ASYNCHRONOUS RESET Write a structural (hierarchical) Verilog code to read an 8-bit message from parallel input (user switches) into a shift-register and use the shift function together with a counter to determine the number of '1's in the message. You have to create a top-level design and initialize shift register and counter explicitly. Do not use if statement (behavioural) approach. (no need for designing the 7-segment LED decoder here, the decoder will be used during the experimental work.)

Fibonacci Series Calculator Verilog VHDL and ModelSim Codes

To achieve a 4-bit Fibonacci Series F(1)=1, F(2)=1 and F(N)=F(N-2)+F(N-1), the Datapath requires certain logic operations including, 2-to-4 Line decoder, 4-bit AND gate, five 4-bit 2-to-1 Multiplexers, five 4-bit registers, two 4-bit 4-to-1 Multiplexers, and 4-bit ALU as depicted in Figure 1. Each logic block of Datapath must be design and simulated separately and imported into the top-level design. The interconnection between each logic block must be done on the top-level design FIBO_DATAPATH using hierarchical design approach. To achieve a 4-bit Fibonacci Series F(1)=1, F(2)=1 and F(N)=F(N-2)+F(N-1), the Datapath requires certain logic operations including, 2-to-4 Line decoder, 4-bit AND gate, five 4-bit 2-to-1 Multiplexers, five 4-bit registers, two 4-bit 4-to-1 Multiplexers, and 4-bit ALU as depicted in Figure 1. Each logic block of Datapath must be design and simulated separately and imported into the top-level design. The interconnection between each logic block must be done on the top-level design FIBO_DATAPATH using hierarchical design approach.

Fibonacci Series Datapath Verilog VHDL and ModelSim Codes

Each logic block of Datapath must be design and simulated separately and imported into the top-level design. The interconnection between each logic block must be done on the top-level design FIBO_DATAPATH using hierarchical design approach. This design should follow a parametric model so that the bit size of the calculator can be adjusted. Write a parameterized Verilog code to define your Datapath. The CLK, and the other control signals should come from the FSM. The FSM control signals and Datapath operations

FSM Design Verilog VHDL and ModelSim Codes

The control unit of this Datapath will be implemented by the FIBO_FSM. FIBO_FSM is divided into two main subcomponents as FSM and FSM_DECO. The FSM will have four external inputs START, ZERO_FLAG, CLK and RST and one output DONE to indicate that the calculation is completed. This component performs all the required control operations providing three outputs as: opcode, operand1 and operand2. The FSM_DECO will use these three outputs as an input and decode the signals as stated in Table 3. The output of the FSM_DECO will be used to control the Fibonacci Series calculation on the Datapath as described in Figure 2.